EST2501 Digital Fundamentals (3): Combinational Logic Circuits

Posted on 2026-05-23 Edited on 2026-09-29 In Exploration Word count in article: 4.1k Reading time ≈ 15 mins.

In this part, we will discuss the basic applications and combinations of logic gates, which are called combinational logic circuits. These circuits take multiple input signals and produce output signals based on the combination of the inputs, without any memory or feedback loops. How to design and simplify the circuit in convenience of combination and cascading will be the main focus of this part.

Collections of EST2501 Digital Electronics notes:

Digital Fundamentals;

Logical Fundamentals;

Combinational Logic Circuit (this article);

Sequential Logic Circuit.

You can find a general introduction to this course in the first article of this series.

Adders

Half Adder

The figure above is the loigc symbol of a half adder. It takes two input bits and , and produces a sum bit and a carry bit .

In other words, the sum bit is the result of adding and without considering any carry from previous bits, while the carry bit indicates whether there is an overflow that needs to be carried to the next higher bit.

With analysis above, the sum and carry bit output can be implemented by an XOR gate and an AND gate respectively. The logic diagram is shown below.

Full Adder

The spirit of designing combinational logic circuits is to break down a complex circuit into smaller, simpler components and to cascade them together.

For a half adder, it can only add two bits and produce a sum and a carry bit; so it is difficult to cascade them to add multiple bits together. To solve this problem, we can design a full adder that takes three input bits: , , and (carry from the previous bit), and produces a sum bit and a carry bit .

The above figure shows the logic symbol of a full adder. The sum bit can be expressed as , and the carry bit can be expressed as .

So, the full adder can be implemented either by using XOR, OR and AND gates, or by using two half adders and an OR gate.

Parallel Adder

With the implement of the full adder, we can cascade them together to design a multi-bit parallel adder. The inputs of each full adder are the corresponding bits of the two numbers to be added, and the carry from the previous full adder. The outputs are the sum bits and the final carry out. A sample 4-bbit parallel adder is shown below.

The parallel provides input and output for carry bits, so it can also be cascaded together to design an adder for even more bits. For instance, with the 4-bit parallel adder above, 8-bit and 16-bit adders can be designed by cascading two and four of the 4-bit adders together respectively.

Carry Look-Ahead Adder

Cascading brings wonderful expansion capability for adders, but it also brings a critical problem: the carry bit has to propagate through all the full adders, which leads to a long delay for the final sum and carry outputs. With the expansion of the number of cascaded full adders, the delay can be even more significant.

To solve this problem, define the carry generation bit and the carry propagation bit . Then, the carry out of each full adder can be expressed as .

With this expression, the carry out of each full adder can be calculated in parallel without waiting for the carry to propagate through all the previous full adders, and each bit of the sum can also be calculated in form of the production and sum of input bits by expanding the expression of recursively. This design is called carry look-ahead adder.

74LS283 is a classical 4-bit carry look-ahead adder integrated circuit, which can be used to design adders for more bits by cascading together.

Comparator

The comparasion of single bits can be implemented by a simple XOR gate, which outputs 0 if the two bits are equal and 1 if they are different.

For nulti-bit comparasion, by listing the truth table, a circuit can be easily designed. The below is the logic structure of a classic 74HC85 4-bit comparator integrated circuit, which provided 3 inputs for previous comparasion results to support cascading together for more bits.

Cascading them is easy - just connect the outputs of one comparator to the cascading inputs of the next comparator, and the final comparasion result can be obtained from the outputs of the last comparator. With this design, comparators for more bits can be easily designed by cascading together more comparators.

Decoder

The name of decoder is a bit confusing, and in my opinion it should be called as a selector. With input in binary code, it selects one of the output lines to be active (1) and all the other output lines to be inactive (0). The figure below shows the logic symbol of a 4-to-16 line decoder, which takes 4 input bits and produces 16 output lines, with only one of them being active at a time.

In this figure and maybe the following ones, the circles on the input or output lines should be paid attention to. They indicate that the signal is active low, which means that the line is active when it is at logic level 0, and inactive when it is at logic level 1. This is a common convention in digital logic design, and it can be used to simplify the circuit design and reduce power consumption.

Another thing to be noticed is single or multiple enable inputs. The enable input is used to control whether the decoder is active or not. - When the enable input is active, the decoder will function normally and produce the output based on the input bits. - When the enable input is inactive, the decoder will ignore the input bits and keep all the output lines inactive.

In decoders, 138 series have 3 enable inputs, while 154 series have only 2 enable input. Take 74LS138 as an example, it has one active-high enable input (G1) and two active-low enable inputs (G2A and G2B). The decoder will only produce an active output when G1 is high and both G2A and G2B are low, i.e., . This allows for more complex control logic to be implemented when using the decoder in a larger circuit.

In 154 series, there are only two active-low enable inputs (G1 and G2), and the decoder will produce an active output when both G1 and G2 are low, i.e., . This design is simpler than the 138 series, but it may require additional logic gates to implement more complex control logic.

The enable input is useful for expansion. For instance, to construct a 5-to-32 line decoder, two 4-to-16 line decoders can be used together. The 5th input bit can be used as the enable input for the two decoders, so that when the 5th bit is 0, the first decoder is enabled and produces outputs for the lower 16 lines, and when the 5th bit is 1, the second decoder is enabled and produces outputs for the upper 16 lines.

Decoders are fundamental building blocks in digital logic design, and they are widely used in various applications such as memory address decoding, data multiplexing, BCD -to-decimal decoding and 7-segment display driving.

Encoder and Priority Encoder

Encoder accepts input in the form of an activation signal in exactly one of the input lines, and produces output in binary code corresponding to the active input line.

However, if the input is not valid, i.e., there are zero or more than one active input lines, the output is undefined. To solve this problem, a priority encoder can be designed, which assigns priority to the input lines and produces output corresponding to the highest priority active input line.

For instance, in a 4-to-2 line priority encoder, if both input lines 0 and 1 are active, the output will correspond to input line 1 because it has higher priority than input line 0. If only input line 0 is active, the output will correspond to input line 0. If no input lines are active, the output can be defined as a specific value (e.g., all zeros) or can be left undefined depending on the design requirements.

The figure above shows the logic symbol of classic 74F148 8-to-3 line priority encoder integrated circuit, which has 8 input lines and produces a 3-bit binary code corresponding to the highest priority active input line. It also has an enable input (EI) and an output valid signal (EO) to indicate whether the output is valid or not.

The priority is assigned from the highest input line (7) to the lowest input line (0), meaning that if multiple input lines are active, the output will correspond to the highest numbered active input line. For example, if input lines 3 and 5 are active, the output will correspond to input line 5 because it has higher priority than input line 3. If only input line 2 is active, the output will correspond to input line 2.

If no input lines are active, the output will be all HIGHs and the output valid signal (EO) will be LOW, indicating that the output is not valid. The enable input (EI) can be used to control whether the priority encoder is active or not. When EI is not activated, the priority encoder will ignore the input lines and produce an output of all HIGHs.

The chip also provides a GS (Group Select) output, which is active low when any of the input lines are active. This can be used for cascading multiple priority encoders together to create a larger priority encoder with more input lines. For example, two 8-to-3 line priority encoders can be cascaded together to create a 16-to-4 line priority encoder, where the GS output of the first encoder is connected to the EI input of the second encoder.

Multiplexer and Demultiplexer

A multiplexer (MUX) is a combinational logic circuit that selects one of several input signals and forwards the selected input to a single output line. The selection of the input signal is controlled by a set of selection lines.

The figure above shows the logic symbol of a classic 74LS151 8-to-1 line multiplexer integrated circuit, which has 8 data input lines (D0 to D7), 3 selection lines (S0 to S2), an active-low enable input (), and two outputs ( and ).

When the enable input is active (i.e., is low), the multiplexer will select one of the 8 data inputs based on the binary value of the selection lines and output it on Y. The output will be the complement of Y. If the enable input is inactive (i.e., is high), both outputs will be inactive (Y will be low and will be high).

A demultiplexer (DEMUX) is the opposite of a multiplexer. It takes a single input signal and routes it to one of several output lines based on the values of selection lines. The figure below shows the logic symbol of a 1-to-8 line demultiplexer, which has one data input line, 3 selection lines, an active-low enable input, and 8 output lines.

The figure below shows how to construct a 1-to-16 line demultiplexer using a 4-16 line decoder.

Parity Generator and Parity Checker

Even parity code and odd parity code are used to detect errors in data transmission. A parity bit is added to a group of bits to make the total number of 1s either even or odd.Single parity code can only detect single-bit error.

We can describe the process of even parity generation as give out 1 if the serial does not have even number of 1s to make the total number of 1s even. In the other words, the even parity generator will generate 1 for those error codes (with odd number of 1s) and generate 0 for those correct codes (with even number of 1s).

As a result, an even parity generator can be considered as an odd parity checker, if we consider the output signal 1 as the true signal, and vice versa.