EST2501 Digital Fundamentals (4): Sequential Logic Circuits

Posted on 2026-05-23 Edited on 2026-09-29 In Exploration Word count in article: 9k Reading time ≈ 33 mins.

Compared with combinational logic circuits, sequential logic circuits have memory and feedback loops, which means that the output not only depends on the current inputs but also on the past history of inputs. In this part, we will discuss the basic building blocks of sequential logic circuits, such as flip-flops and registers, and how to design and analyze more complex sequential circuits like counters and finite state machines.

Sequential logic circuits can be classified into three types based on their behavior: - Bistable device has two stable states and can store one bit of information. It can be implemented using flip-flops, which are the basic building blocks of sequential logic circuits. - Monostable device has one stable state and one unstable state. It can be implemented using a simple RC circuit or a 555 timer. - Astable device has no stable states and continuously oscillates between two states. It can be implemented using a 555 timer or a pair of cross-coupled NAND gates.

Collections of EST2501 Digital Electronics notes:

Digital Fundamentals;

Logical Fundamentals;

Combinational Logic Circuit;

Sequential Logic Circuit (this article).

You can find a general introduction to this course in the first article of this series.

Latches

Latch is a kind of bistable device that can store one bit of information. It has two inputs, usually called Set and Reset, and one output.

The difference between a latch and a flip-flop is that a latch is level-sensitive, meaning that it changes its output as long as the input is active, while a flip-flop is edge-sensitive, meaning that it changes its output only at the moment of a clock edge.

Set-Reset Latch

Set-Reset Latch, or SR Latch, is the simplest type of latch. It can be implemented using two cross-coupled NOR gates or two cross-coupled NAND gates. It has two inputs, Set (S) and Reset (R), and one output (Q). The behavior of the SR Latch can be described by the following truth table:

State	S	R	Q
Hold	0	0	Q
Set	1	0	1
Reset	0	1	0
Invalid	1	1	X

The circuit diagram of active-HIGH input S-R latch and active-LOW input - latch are shown above.

An enable input can be added to the SR latch to control when the latch can change its state. This is called an Gated SR Latch. The circuit diagram is shown below.

When the enable input (EN) is active, the gated SR latch behaves like a normal SR latch. When the enable input is inactive, the outputs Q and will hold their previous state regardless of the inputs S and R. This is level-triggered behavior, which is a characteristic of latches.

Flip-Flops

Flip-Flop is synchronous bistable device, which means that it changes its state only at the moment of a clock edge. In other words, a flip-flop is actually a gated latch that is triggered by a clock signal.

The above is a simplified logic diagram for a positive edge-triggered SR flip-flop. To ensure that the flip flop changes state only at the moment of a clock edge, we use a pulse transition detector to generate a short pulse when the clock signal transitions from low to high, and apply this pulse to enable the steering gates (G1 and G2) that control the inputs to the latch. This way, the latch will only respond to the inputs S and R during the short pulse generated by the clock edge, effectively making it an edge-triggered flip-flop.

The logic diagram of the pulse transition detector is shown below. Here, the propagation delay of the inverter should be considered.

D Flip-Flop

The D flip-flop, also known as the data or delay flip-flop, is a type of flip-flop that has a single data input (D) and a clock input (CLK). The output Q takes the value of the input D at the moment of the clock edge. The behavior of the D flip-flop can be described by the following truth table:

State	CLK	D	Q
RESET	↑	0	0
SET	↑	1	1

In other words, D flip-flop is a special case of SR flip-flop where the S and R inputs are connected to the D input and its complement, respectively. This ensures that the invalid state of the SR flip-flop is never reached, making the D flip-flop more reliable and easier to use in digital circuits. The logic diagram of a D flip-flop is shown as below.

JK Flip-Flop

The JK flip-flop is a more versatile type of flip-flop that has two inputs, J and K, and a clock input (CLK). The behavior of the JK flip-flop can be described by the following truth table:

State	CLK	J	K	Q
HOLD	↑	0	0	Q
SET	↑	1	0	1
RESET	↑	0	1	0
TOGGLE	↑	1	1

The logic diagram of a JK flip-flop is shown below.

An activate-LOW preset and clear inputs can be added to the JK flip-flop to allow asynchronous setting and resetting of the output. The former input will set the output Q to 1 when activated, while the latter input will reset the output Q to 0 when activated, regardless of the clock signal or the J and K inputs.

Characteristics of Flip-Flops Operation

The time interval between the 50% point on the triggering edge of the clock signal and the 50% point on the LOW-to-HIGH transition of the output Q is called the propagation delay time from LOW to HIGH (), while the time interval between the 50% point on the triggering edge of the clock signal and the 50% point on the HIGH-to-LOW transition of the output Q is called the propagation delay time from HIGH to LOW ().

The time interval between the 50% point on the triggering edge of the clock signal and the 50% point on the data input D is called the set-up time (). The data input D must be stable during this time interval before the clock edge to ensure that the flip-flop can correctly capture the input value.

Similarly, the time interval between the 50% point on the triggering edge of the clock signal and the 50% point on the data input D is called the hold time (). The data input D must be stable during this time interval after the clock edge to ensure that the flip-flop can correctly capture the input value.

One-shot

A one-shot, also known as a monostable multivibrator, is a type of circuit that generates a single output pulse of a specified duration in response to an input trigger. The output pulse is generated when the input signal transitions from low to high (or from high to low, depending on the design). The duration of the output pulse is determined by the circuit components and can be adjusted as needed.

The diagram above shows a simple one-shot circuit. When the trigger signal is applied, the output Q goes high for a certain duration determined by the resistor R and capacitor C, and then returns to low.

The pulse width of a one-shot is the time interval during which the output remains in the high state after receiving the trigger signal. The pulse width can be calculated using the following formula: where is the resistance, is the capacitance, is the supply voltage, and is the threshold voltage at which the output transitions from high to low.

Non-retriggerable One-shot

A non-retriggerable one-shot is a type of one-shot circuit that does not allow the output pulse to be extended or retriggered by additional input triggers while the output is still high. In other words, once the output pulse is generated, it will complete its duration regardless of any subsequent triggers until it returns to low.

The above is the ANSI/IEEE standard logic symbol of 74LS121, a classic non-retriggerable one-shot. The inputs A1 and A2 are the trigger inputs combined with a OR gate, while the input B is an active-LOW reset input. The output Q goes high for a certain duration when either A1 or A2 receives a trigger signal, and it returns to low when the reset input B is activated or when the pulse duration expires.

If we do not want to use the internal resistor, we can connect the external resistor with (Pin 11) and . Similarly, for the external capacitor, we can connect it to Pin 11 and (Pin 10). If internal resistor is used, connect (Pin 9) to .

The , and are connected with a strange device - a Schmitt trigger. A Schmitt trigger is a type of comparator circuit that incorporates hysteresis, which means it has two different threshold voltage levels for switching between high and low output states. It will only change its output state when the input signal crosses the upper threshold voltage (for a rising input) or the lower threshold voltage (for a falling input). This makes it ideal for use in one-shot circuits, as it ensures that the output pulse is generated only in response to a valid trigger signal, and not due to noise or glitches on the input.

So, the final internal trigger signal can be expressed as:

Retriggerable One-shot

74LS122 is a retriggerable one-shot, which means that if a new trigger signal is received while the output is still high, the output pulse will be extended by resetting the timing interval. This allows for continuous triggering without waiting for the previous pulse to complete.

The structure of 74LS122 is similar to that of 74LS121, but it uses a different internal configuration to allow for retriggering.

When the chip does not connect to external resistor and capacitor, the pulse width can be calculated using the following formula: where is the internal resistance and is the internal capacitance.

If external components are used, the pulse width can be calculated using the following experience formula: where is the external resistance and is the external capacitance. In this formula, the units of and should be in kilo-ohms and picofarads, respectively, to get the pulse width in nanoseconds.

555 Timer

The 555 timer is a widely used integrated circuit that can be configured in various modes, including Schmitt trigger, monostable (one-shot), astable (oscillator), and bistable (flip-flop) modes.

The diagram above shows the internal structure of a 555 timer. Here, we introduce two new basic components.

The first device in shape of triangle is a comparator, which compares the input voltage of the upper and lower input. If the voltage at the upper input is higher than that at the lower input, the output of the comparator will be high; otherwise, it will be low. The two comparators in the 555 timer are used to compare the voltage across the capacitor with two reference voltages (1/3 and 2/3 of the supply voltage) to determine when to set or reset the flip-flop.

The second device is a discharge transistor. When the base of the transistor receives a high signal from the flip-flop, it turns on and allows current to flow from the capacitor to ground, effectively discharging the capacitor. This is used to reset the timing interval in monostable mode or to create a square wave in astable mode.

One-shot Mode

The pulse width of the one-shot mode can be calculated using the following formula: where is the resistance of the timing resistor and is the capacitance of the timing capacitor. The control voltage pin can be used to adjust the threshold voltage levels, which in turn can affect the pulse width. However, in most applications, the control voltage pin is left unconnected or connected to ground through a capacitor for noise filtering.

Astable Mode

In the astable mode. the 555 timer will repeat the following cycle indefinitely: - The path charges the capacitor until the voltage across it reaches 2/3 of , at which point the upper comparator triggers and sets the flip-flop, causing the discharge transistor to turn on and discharge the capacitor through . - The capacitor discharges until the voltage across it drops to 1/3 of , at which point the lower comparator triggers and resets the flip-flop, causing the discharge transistor to turn off and allowing the capacitor to start charging again.

The frequency of the oscillation can be calculated using the following formula: where and are the resistances of the timing resistors and is the capacitance of the timing capacitor. The duty cycle of the output waveform can be calculated using the following formula: where is the duty cycle expressed as a fraction (e.g., 0.5 for 50%).

Schmitt Trigger

It is easy to see that the Schmitt trigger is essentially a 555 timer without the discharge transistor and the flip-flop. The output of the Schmitt trigger will be high when the input voltage is above the upper threshold (2/3 of ) and low when the input voltage is below the lower threshold (1/3 of ). The hysteresis provided by the two thresholds helps to prevent noise from causing false triggering, making it ideal for use in applications such as signal conditioning and debouncing.

Sequential Logic Circuits

Above is the general structure of a sequential logic circuit. A sequential logic circuit is called Moore sequential circuit if the output signals depend only on the internal states of the system, and it is called Mealy sequential circuit if the output signals depend on both the current input signals and the current state signals.

The combinational logic network takes the current state signals and the input signals as inputs and produces the output signals and the next state signals as outputs. The flip-flops (FF) are used to store the current state signals, which are updated on each clock cycle based on the next state signals produced by the combinational logic network.

Counters

Designing a counter is a common application of sequential logic circuits. In synchronous counters, all flip-flops are triggered by the exact same clock signal, which means that all state changes occur simutaneously. In contrast, in asynchronous counters, the flip-flops are triggered by clock signals that are generated by the output of the previous flip-flop.

Asynchronous Counter

A 10-count asynchronous counter, designed with D-filp-flops, are shown below.

In asynchronous counters, the end signal for the -digital counter is exactly . In other words, take 10-count counter as an example, the end signal is 10, which means that the system will generate a glitch signal of 10 when the counter reaches 10, and this signal can be used to reset the counter back to 0. However, due to the nature of asynchronous counters, there may be a short period of time during which the output signals are in an indeterminate state (glitch) when the counter transitions from one state to another, especially when multiple bits change simultaneously.

The end signal for 10-count is 10, or 1010 in binary. However, in the NAND gate implementation of the counter, only the second and the fourth bits are used to generate the end signal. This is partial decoding: since the combination of 11 in second and fourth bits will never occur in the counting sequence of a 10-count counter, we can use this combination to generate the end signal without affecting the normal counting sequence. This allows us to use fewer gates and simplify the circuit design. For instance, if we want to construct a 12-counter, only the third and the fourth bits are used to generate the end signal.

This 12-module counter is designed differently with JK-FFs instead of D-FFs, and the end signal is generated by a SR latch instead of simply using NAND gates. It is noticed that, by introducing the SR latch, in the CLK cycle when the counter reaches 12, the former part of the CLK cycle will remain 12 in counter, and the latter part of the CLK cycle will reset the counter to 0.

However, why we still substitute the NAND gate with a SR latch? The reason is different propagation delay of each JK-FFs. Suppose when a end signal is generated, only the fourth JK-FFs complete the state transition. In this state, the output of the counter is 8, and the end signal will not continue anymore, since current state of the counter is not 12. This will cause the counter to be stuck at 8, which is a problem. By using a SR latch, we can ensure that once the end signal is generated, it will remain high until the counter is reset to 0, thus preventing the counter from being stuck at an incorrect state.

The figure above shows the structure of 74HC93, which is a classic 16-modulo asynchronous counter. This chip is consist actually of two separate counters: a 1-bit binary counter (the first four JK-FFs) and a 3-bit binary counter (the last three JK-FFs).

For clear inputs, the chip provides two separate clear inputs: RO(1) for the first counter and RO(2) for the second counter and they are connected to active-LOW clear inputs of each JK-FF with a NAND gate.

Synchronous Counter

Asynchronous counters have the disadvantages of glitches and cascaded propagation delay, which can be solved by using synchronous counters.

Above is the structure of a 16-modulo synchronous counter. It is noticed that the clock signal is directly connected to all flip-flops, which means that all flip-flops are triggered simultaneously. The combinational logic network is used to generate the J and K inputs for each flip-flop based on the current state of the counter, ensuring that the counter counts correctly without any glitches or propagation delay issues.

For example, if we want to construct a 12-modulo synchronous counter, the end signal is generated in status 11.

Classic synchronous counters include 74HC161, 74HC163, and 74HC193. Some new inputs include: - (synchronous): active-LOW load input, which can be used to load a specific value into the counter. - (asynchronous): active-LOW clear input, which can be used to reset the counter to zero. - (asynchronous), or enable parallel pin only controls the internal counting logic. It determines whether the flip-flops are allowed to change state. It has absolutely no effect on the RCO pin. - (asynchronous), or enable trickle pin, controls the internal counting logic and also gates the RCO. - (asynchronous): active-LOW ripple carry output, which indicates when the counter has reached its maximum count and is about to roll over to zero. This can be used for cascading multiple counters together to create a larger counter.